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1N270 74LS00

This figure shows the schematic diagram of the simple inductance meter. U1, a 74LS00 two-input quad NAND gate logic integrated circuit, two resistors, a capacitor, and a surplus microprocessor crystal form a stable crystal oscillator near the marked frequency of the crystal. The RF voltage is taken from pin 8 through isolation capacitor C3 to the measuring circuit. RF voltage is applied through capacitor C7 to J1, a bindiftg post. This same RF voltage is applied to a resistive voltage divider consisting of R3 and R4. Germanium diode D1 has its anode connected to the junction between R3 and R4. RF across the variable tuning capacitor C6 is applied back through C5 to the cathode of D1 and load resistor R5, the lower end of which is bypassed to ground through C4 and applied to the positive terminal of meter M1. R6 is a sensitivity control connected between the negative terminal of meter M1 and ground. This instrument operates by measuring the RF voltage developed across C6, which will be the highest when the series circuit made up of C6 and the unknown inductance is at resonance at the crystal frequency. In other words, the value of the unknown is indicated on the dial attached to C6 when the voltage indicated by M1 peaks, just the opposite of bridge operation.

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