NE555 LM339N CD4011 1N4001 ZTX750 BC107A 1N5400
The PWM model train controller shown offers results that are far superior to those of a traditional rheostat-type model train controller and provides better fine control of train speeds. A 555 timer chip (IC1) is configured as a free-running oscillator operating at 80 kHz. The exponential ramp waveform generated across capacitor C3 feeds a comparator (IC2), whose threshold reference is set by logarithmic potentiometer VR1. The output of comparator IC2 is inverted by IC3a and IC3b and it drives the output stage, which comprises transistors TR1 and TR2; the latter can handle 2 A and dissipate 1 W, which is more than adequate for a saturated switch operation. Diode D2 protects against back BMP in the train motor. Short-circuit protection is provided with a 0.5-Ω series sense resistor (R8/R9). Transistor TR3 switches on when the current flowing reaches approximately 1.2 A. This sets the out-put of an S-R flip-flop (IC3c/lC3d) low. LED D3 illuminates to indicate a fault, and TR1 is disabled by the inverters. Capacitor C4 introduces a short time period across TR3 to prevent the cutout from triggering falsely. Push-switch S1 is a "kick" button. Pressing this causes a short, higher-voltage burst to be applied to reluctant motors.