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74HC161 74HC4024 CD4001BE

74HC161 74HC4024 CD4001BE

The circuit diagram for a simple frequency generator that uses a divide-by-N counter, based on a single 74HC161, is shown. Although IC1a and IC1b are NOR gates, in this circuit, they are used as inverters in a crystal clock generator. This provides an accurate 2-MHz output signal that is fed to the input of the divide-by-N circuit based on IC2 and IC1c. An inversion is needed between the comparator output and the negative active preset enable input, and this inversion is provided by IClc.Unfortunately, setting the division rate is more convoluted than simply writing the required value for N to the data inputs (D0 to D3). Table 1 shows the division rates and output frequencies for the 16 input codes for IC2. If the data inputs of IC2 are controlled via inverters, the division rate is one more than the value written to the port. Without a hardware inversion, a software inversion is required.This is actually quite easy, and it is just a matter of deducting the required division rate from 16 (e.g., for a division rate of 4, a value of 12 is written to IC2). Notice that the minimum division rate is 2, and that writing a value of 15 to IC2 will not give a division by 1.

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