Altera Corporation Core Version a.b.c variable 4–1
July 2004 Preliminary
Chapter 4. Serial Configuration
Devices (EPCS1, EPCS4,
EPCS16 & EPCS64) Data Sheet
Features
The serial configuration devices provide the following features:
■ 1-, 4-, 16-, and 64-Mbit flash memory devices that serially configure
Stratix
?
II FPGAs and the Cyclone? series FPGAs using the active
serial (AS) configuration scheme
■ Easy-to-use four-pin interface
■ Low cost, low pin count and non-volatile memory
■ Low current during configuration and near-zero standby mode
current
■ 3.3-V operation
■ Available in 8-pin and 16-pin small outline integrated circuit (SOIC)
package
■ Enables the Nios
?
processor to access unused flash memory through
AS memory interface
■ Re-programmable memory with more than 100,000 erase/program
cycles
■ Write protection support for memory sectors using status register
bits
■ In-system programming support with SRunner software driver
■ Programming support with USB Blaster? or ByteBlaster? II
download cables
■ Additional programming support with the Altera
?
Programming
Unit (APU) and programming hardware from BP Microsystems,
System General, and other vendors
■ Software design support with the Altera Quartus
?
II development
system for Windows-based PCs as well as Sun SPARC station and
HP 9000 Series 700/800
■ Delivered with the memory array erased (all the bits set to 1)
1 Whenever the term “serial configuration device(s)” is used in
this document, it refers to Altera EPCS1, EPCS4, EPCS16, and
EPCS64 devices.
Functional
Description
With SRAM-based devices such as Stratix II FPGAs and the Cyclone
series FPGAs, configuration data must be reloaded each time the device
powers up, the system initializes, or when new configuration data is
needed. Serial configuration devices are flash memory devices with a
C51014-2.0
