SN74ALVCH32245

This 32-bit noninverting bus transceiver is designed for 1.65-V to 3.6-V V_CC operation. The SN74ALVCH32245 is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements.

This device can be used as four 8-bit transceivers, two 16-bit transceivers, or one 32-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH32245 is characterized for operation from –40°C to 85°C.

Supply voltage range, V _CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, V _I: Except I/O ports (see Note 1) . . . . . . . . . . . . –0.5 V to 4.6 V
I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V_CC + 0.5 V
Output-voltage range, V_O (see Notes 1 and 2) . . . . . . . . . . . . . . –0.5 V to V_CC + 0.5 V
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . –50 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . –50 mA
Continuous output current, I_O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θ_JA (see Note 3) . . . . . . . . . . . . . . . .. . . . . . . . . . 40°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . .  . . . . . . . . . . . . . –65°C to 150°C

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.  hese are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated   nditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V  aximum. 3. The package thermal impedance is calculated in accordance with JESD 51.

·Member of the Texas Instruments Widebus+™ Family
·EPICE™(Enhanced-Performance Implanted CMOS) Submicron Process
·Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
·Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
·ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)
·Packaged in Plastic Fine-Pitch Ball Grid Array Package