SN75LVDS84
FLATLINKE TRANSMITTERS

Abstract

SN75LVDS84, SN75LVDS85
FLATLINK? TRANSMITTERS


SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999
1POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265
C0068 21:3 Data Channel Compression at up to
163 Million Bytes per Second Throughput
C0068 Suited for SVGA, XGA, or SXGA Data
Transmission From Controller to Display
With Very Low EMI
C0068 21 Data Channels Plus Clock In
Low-Voltage TTL and 3 Data Channels Plus
Clock Out Low-Voltage Differential
C0068 Operates From a Single 3.3-V Supply and
250 mW (Typ)
C0068 5-V Tolerant Data Inputs
C0068 ESD Protection Exceeds 6 kV
C0068 SN75LVDS84 Has Falling Clock-Edge
Triggered Inputs, SN75LVDS85 Has Rising
Clock-Edge-Triggered Inputs
C0068 Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal
Pitch
C0068 Consumes Less Than 1 mW When Disabled
C0068 Wide Phase-Lock Input Frequency Range:
31 MHz to 68 MHz
C0068 No External Components Required for PLL
C0068 Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA-644 Standard
C0068 Improved Replacement for the DS90C561

description
The SN75LVDS84 and SN75LVDS85 FlatLink transmitters each contain three 7-bit parallel-load serial-out shift
registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single
integrated circuit. These functions allow 21 bits of single-ended low-voltage TTL (LVTTL) data to be
synchronously transmitted over three balanced-pair conductors for receipt by a compatible receiver, such as
the SN75LVDS82 or SN75LVDS86.
When transmitting, data bits D0 – D20 are each loaded into registers of the SN75LVDS84 upon the falling edge
and into the registers of the SN75LVDS85 on the rising edge of the input clock signal (CLKIN). The frequency
of CLKIN is multiplied seven times and then used to unload the data registers in 7-bit slices and serially. The
three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency
of CLKOUT is the same as the input clock, CLKIN.
AVAILABLE OPTIONS
?
LATCHING CLOCK EDGE
FALLING RISING
SN75LVDS84DGG
SN75LVDS84DGGR
SN75LVDS85DGG
SN75LVDS85DGGR
?
The R suffix indicates taped and reeled packaging.
Copyright ? 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments Incorporated.
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D4
V
CC
D5
D6
GND
D7
D8
V
CC
D9
D10
GND
D11
D12
NC
D13
D14
GND
D15
D16
D17
V
CC
D18
D19
GND
D3
D2
GND
D1
D0
NC
LVDSGND
Y0M
Y0P
Y1M
Y1P
LVDSV
CC
LVDSGND
Y2M
Y2P
CLKOUTM
CLKOUTP
LVDSGND
PLLGND
PLLV
CC
PLLGND
SHTDN
CLKIN
D20
DGG PACKAGE
(TOP VIEW)
NC – Not Connected